1. Field of the Invention
The present invention relates to the field of computer systems, in particular, computer systems that support multiple instruction operation sizes. More specifically, the present invention relates to optimizations performed by compilers of these computer systems.
2. Background
Many computer systems support multiple instruction operation sizes. Beside different instructions, such as Add verses Load, having different instruction operation sizes, an instruction, such as Load, may be supported in different instruction operation sizes, such as 8 bit Loads with or without sign extend, 16 bit Loads with or without sign extend, and 32 bit Loads, Additionally, it is not uncommon that instruction operations of a particular size, such as 16 bit instruction operations, are less efficient than instruction operations of another size, such as 32 bit instruction operations. Also, zero extended loads are more efficient than sign-extended loads. Traditionally, the way compilers handle the smaller data, i.e. those smaller than a word, is to sign-extend or zero-extend the data, depending on their types, making each one of them a word long, even though some of the extensions are unnecessary. For example, on a computer system having 32-bit word size, a traditional compiler would extend the instruction operation size of an instruction producing a value to 32 bits even if all uses of the value only depend on the rightmost eight bits.
Thus, it is desirable if a compiler in generating code for a particular target machine can optimize the instruction operation sizes of the various instruction operations in the generated code, avoiding unnecessary extensions of smaller data, and the less efficient instruction operations. As will be disclosed, the present invention provides a method and apparatus for optimizing instruction operation sizes of various instructions in the generated code of a compiled program that achieves the desired results described above.